The present invention relates to automatic test equipment for testing integrated electronic circuits and, more particularly, to those test systems testing advanced high performance devices such as RISC electronic circuits or electronic circuits with Phase Locked Loops ("PLL").
With the development of new, superpipelined high performance RISC processors, such as Digital Equipment Corporation's 21064 (also known as the Alpha AXP) and MIPS' R4000/4400 processors, new problems concerning the testing of these devices have surfaced. These devices cannot tolerate having power applied to them without any functional stimulus input. Applying power to these devices without any functional stimulus input can force these devices into a catastrophic high power dissipation mode, causing severe damage to the internal circuitry of the device under test. This problem was never experienced with the LSI/VLSI devices prior to these high performance devices. The above situation can be better understood by explaining the operation of modern LSI/VLSI testers.
In modern LSI/VLSI testers, when a functional test is initiated, the test vectors stored in the tester's local memory are executed beginning at some programmed start location. The test vectors are formatted and timing is applied from the timing generators. Thereafter, the timed, formatted test vector is applied to the device under test. When a functional failure occurs, the functional test is typically aborted, which means that no further stimulus is applied to the device. In some testers, equipped with a special error capture memory, the failure can be logged into the capture memory and testing can continue uninterrupted. In either case (i.e., with or without capture memory), when the last test vector in the truth table is executed, the application of any further test vectors is stopped (i.e. no further stimulus is applied to the device). At this point, if power is not quickly removed from the class of devices mentioned above, the device would be damaged by the test system.
During device testing and/or characterization, there are many situations where a perfectly good device will fail a functional test. For instance, this frequently happens when performing a speed sorting of devices when the test program attempts to run the functional test at the highest speed bin required. If the device is not fast enough, it will fail at some random point during the functional test.
One way to solve the above problem is to disconnect the power to the device under test. However, this solution may not be feasible in many instances. For example, when performing a timing margin characterization or a shmoo plot on a device, many functional failures are generated on a good device while the test system is converging upon the pass/fail boundary of device operation. In this case, a 512.times.512 points shmoo plot requires that 262,144 separate functional tests be performed on the device. For the class of devices mentioned above, that many power up/power down cycles would be required so as to not damage the device. If we assume that it requires 1 millisecond to perform a power up, or a power down cycle, the shmoo plot would require almost 9 minutes of tester time for cycling power on the device under test. Clearly, this results in a very high amount of unproductive and wasted time which adds to the overhead cost of testing operations.
Currently, none of the existing testers address the above problem in entirety. However, distantly related features have appeared in prior generations of ATE systems to solve other testing problems.
For instance, the Fairchild Sentry 600 line of testers (presently owned by Schlumberger Technologies, Inc., the present assignee) include a mode whereby the test program could define a "minor loop" of test vectors as illustrated in prior art FIG. 1. FIG. 1 illustrates a local memory 30 which stores a series of test vectors to be applied to the device under test ("DUT"). The program will load a start address register 34 to indicate a start of the test at an address location 32. The program will specify a minor loop between address locations 36 and 40 at some predefined period in a program. This minor loop is reached through sequential execution, as illustrated by line 38.
A typical use for such a minor loop is when older PMOS and NMOS microprocessors were tested. The test program would run through a first series of test vectors, and then would want to reload another series. During the reloading, the minor loop maintains signal stimulus to the internal memory of the PMOS and NMOS devices so that they do not lose their state. When the new test vectors have been loaded in, the test program will cause the minor loop to be exited by loading a value into an appropriate mode register, which is then operative on the next clock cycle in the test. After the minor loop is exited, the test vectors are executed again until address 42 specified by stop address register 44 is reached to indicate the end of the test.
Additionally, devices which incorporate phase lock loops ("PLLs") can also use this capability, so as to keep the PLL frequency from drifting while new test vectors are being loaded into the pattern memory.
It should be noted that the "minor loop" function can only be activated if the test vector execution reaches the beginning location of the loop. If the test vector execution does not somehow reach these locations (i.e., the device under test fails at an earlier location), then the test pattern never enters into this loop. Newer test system architectures now allow for either multiple loop locations, or the indefinite repetition of single vectors to accomplish the same functions. However, it is still necessary to have the test vector execution reach the locations of these loops or single vector repeats. In this system, once the "minor loop" is invoked, local memory is available for modification by the test program, but the timing system continues to be used and therefore new program values cannot be entered into the timing generators.
A second system uses a second scheme incorporating a "Free Running Clock" ("FRC") 50, as shown in prior art FIG. 2. This scheme was first developed and used on the Schlumberger S20/S21 series of testers. The FRC 50 is applied to the clock input of the DUT through multiplexing circuitry 52. The timing values in memories 54 are applied to the pins through timing generators 56 under the control of a test period generation circuit 58, which is in turn programmed by a test period memory 60. After a functional test is run, the memories 54 are reloaded with DC parametric tests to be applied to the DUT. The FRC continues to run to apply clock signals to the DUT, which are needed for running the DC tests. Since the FRC is now unsynchronized with any test vectors, if a new functional test was to be applied (as opposed to a DC test), the whole system would have to be shut down and restarted. There is no provision for resuming from the last state the DUT was in, since the FRC is unsynchronized after the first functional test ends. The FRC 50 is started coherently with the timing generators 56 on the beginning of the functional test, but after the functional test ends, there is no longer synchronization. This sharply curtails the use of an FRC. Generally, in this system, the local memory is also available for program modifications, as well as all of the timing generators, except for the FRC generator which cannot be reprogrammed since it is being utilized.
On the other hand, the present invention offers a new tester feature which is not offered by the existing ATE systems. The present invention is designed to address the above problems in testing the latest generation of high performance RISC processors. The invention enables a test system to maintain functional input stimulus to a device under test, while it is reprogramming a new test sequence or while it is addressing a device failure. This is done in a manner that is synchronized with the regular functional tests applied to the device under test.